1. Field of the Invention
The present invention relates to an electrically programmable nonvolatile semiconductor memory device, and more specifically, to a nonvolatile semiconductor memory device requiring programming before erasure. More specifically, it relates to a nonvolatile semiconductor memory (Flash Memory) allowing collective erasure.
2. Description of the Background Art
FIG. 59 is a schematic cross section of a conventional nonvolatile memory cell. Referring to FIG. 59, the memory cell includes a drain region 2 and a source region 3 formed of impurity regions of high impurity concentration in a main surface of a semiconductor substrate 1, a floating gate 6 formed on a channel region 4 between drain region and source region 3 with a gate insulating film 5 interposed therebetween, and a control gate 8 formed on floating gate 6 with an interlayer insulating film 7 interposed therebetween. Floating gate 6 is surrounded by an insulating film, and the memory has a so called "floating gate type transistor" structure.
Threshold voltage of the memory transistor changes dependent on the amount of charges (electrons) stored in floating gate 6. Injection and extraction of electrons to and from floating gate 6 is carried out in the following manner.
(i) Injection of Electrons
For injecting electrons to floating gate 6, a programming high voltage Vpp is applied to control gate 8, programming voltage VBL is applied to drain region 2, and ground potential is applied to source region 3. Under this voltage condition, a high electric field is generated near drain region 2, and electrons flowing from drain region 2 to source region 3 are excited to be hot electrons. The hot electrons are accelerated by the high electric field generated by the high voltage applied to control gate 8, and jump over the potential barrier of gate insulating film 5 to be injected to floating gate 6 to be stored therein. With electrons injected in floating gate 6, the threshold voltage of the memory cell is shifted to the higher voltage side. As shown in FIG. 60 this state is referred to as "programmed state", which corresponds to a state storing information "0".
(ii) Extraction of Electrons
For extracting electrons from floating gate 6, ground potential is applied to control gate 8, drain region 2 is set to a floating state, and programming high voltage Vpp is applied to source region 3. In this state, a high electric field is generated between floating gate 6 and source region 3, and due to Fouhler-Nordheim tunnelling current, electrons are extracted from floating gate 6 to source region 3. With electrons extracted from floating gate 6, threshold voltage of the memory cell transistor is shifted to the lower voltage side. This state, which is shown in FIG. 60, is referred to as "erased state" which corresponds to the state storing information "1".
More specifically, a nonvolatile memory cell stores information "1" or "0" in accordance with the amount of electrons stored in floating gate 6.
In normal operation, data is read in the following manner. A selecting voltage VR at the level of a supply voltage Vcc is applied to control gate 8 of the selected memory cell. Assume that the memory cell is now at the programmed state and has the threshold voltage of Vth1, as shown in FIG. 60, the memory cell transistor is non-conductive, and current does not flow between the drain and the source. If the memory cell is at the erased state, the threshold voltage thereof is Vth2, so that the transistor is rendered conductive and current flows between drain region 2 and source region 3. Information is read by detecting presence/absence of the current Id flowing between drain region 2 and source region 3.
FIG. 61 is a block diagram showing the whole structure of a conventional nonvolatile semiconductor memory device. Referring to FIG. 61, the nonvolatile semiconductor memory device includes a memory array 10 having a plurality of memory cells MC arranged in a matrix of rows and columns. Memory array 10 includes word lines WL to each of which a row of memory cells are connected, and a plurality of bit lines BL to each of which a column of memory cells MC are connected. In FIG. 61, only one memory cell MC is shown as a representative, which is arranged corresponding to a crossing of one bit line BL and one word line W1. The memory cell MC has the structure shown in FIG. 59, and it has its control gate connected to a corresponding word line WL and its drain region connected to a corresponding bit line BL. The source region of the memory cell MC is connected to a source line SL. The source line SL is arranged common to all the memory cells.
The nonvolatile semiconductor memory device further includes an address buffer 12 receiving an external address EXA0 to EXAn for generating an internal address, a row decoder 14 decoding the internal row address from address buffer 12 for generating a word line selecting signal for selecting a corresponding word line in memory cell array 10, a column decoder 16 decoding an internal column address from address buffer 12 for generating a column selecting signal for selecting a corresponding column of memory array 10, a high voltage switch 18 responsive to a row selecting signal from row decoder 14 for transmitting a programming high voltage or a selecting voltage to the selected word line, and a Y gate 20 responsive to the column selecting signal from column decoder 16 for selecting a corresponding bit line of memory array 10. High voltage switch 18 transmits a programming high voltage Vpp to the selected word line in writing operation, and transmits a selecting voltage at the level of the supply voltage Vcc to the selected word line in normal reading operation.
The nonvolatile semiconductor memory device further includes an input/output buffer 22 for inputting/outputting data from and to the outside of the device, a programming circuit latching write data from input/output buffer 22 and generating a programming voltage corresponding to the write data, and a sense amplifier for reading information by detecting presence/absence of a current on the selected bit line during data reading. The programming circuit and the sense amplifier are represented by one block 24 in FIG. 61.
The nonvolatile semiconductor memory device further includes a control signal buffer 26 receiving externally applied control signals for generating internal control signals, a control circuit 28 for generating necessary control signals in accordance with the internal control signals from control signal buffer 26, a high voltage control circuit 30 receiving an externally applied high voltage Vpp for generating a programming high voltage and a programming voltage, and an array source switch 32 for setting the potential of source line SL to the ground potential or to the level of the programming high voltage under the control of control circuit 28. The programming high voltage generated from high voltage control circuit 30 is transmitted to high voltage switch 18 and to array source switch 32, while the programming voltage (VBL) is transmitted to programming circuit (block 24).
Control circuit 28 is shown controlling operations of the write circuit and sense amplifier block 24, row decoder 14, column decoder 16 and address buffer 12. The operation will be described.
The operation of the nonvolatile semiconductor memory device includes programming, erasure and reading. Before programming, it is necessary to erase all the information stored in all the memory cells, that is, all memory cells must be erased.
(i) Programming:
At the time of programming, an address signal designating a memory cell to which data is to be written is applied to address buffer 12, and a control signal enabling data writing is applied to control signal buffer 26.
A high voltage Vpp is applied to high voltage control circuit 30. High voltage control circuit 30 generates a programming high voltage from the applied high voltage and applies the generated voltage to high voltage switch 18, and it also generate programming voltage VBL and applies the same to programming circuit (block 24). Under control of control circuit 28, input/output buffer 22 takes in an externally applied data signal, generates and applies to block 24 an internal write data. In block 24, the programming circuit latches the applied data.
The internal row and column address signals applied from address buffer 12 are decoded by row decoder 14 and column decoder 16, respectively, and a row selecting signal and a column selecting signal are generated. High voltage switch transmits the programming high voltage applied from high voltage control circuit 30 to the selected word line in response to the row selecting signal from row decoder 14. Y gate 20 connects a corresponding bit line to block 24 in response to the column selecting signal from column decoder 16. The programming circuit sets the potential of the selected bit line in accordance with the latched data signal. If the write data is "0", the programming voltage VBL applied from high voltage control circuit 30 is transmitted to the selected bit line. If write data is "1", the potential of 0 V is transmitted to the selected bit line.
In array source switch 32, the source line SL is set to the ground potential (0 V) under the control of control circuit 28. Consequently, when information "0" is to be written in the selected memory cell, electrons are injected to the floating gate. Meanwhile, if information "1" is to be written, the potential on the bit line is at the ground potential (0 V), and if the programming high voltage Vpp is applied to the control gate, a high electric field is not generated near the drain, hot electrons are not generated, and electrons are not injected to the floating gate either. In other words, it corresponds to the erased state (erasing operation is carried out without fail before data writing).
(ii) Erasure:
Erasure includes programming before erasure in which information "0" is written to all memory cells, and collective erasing operation in which information "1" is written to all memory cells. More specifically, the threshold voltage of all memory cells is once set to a high threshold voltage state, and then all memory cells are erased collectively.
In programming before erasure, addresses are successively generated from address buffer (the addresses may be externally applied, or the addresses may be generated using an internal address counter), and the generated addresses are applied to row decoder 14 and column decoder 16. In the programming circuit (block 24), information "0" is latched under the control of control circuit 28. Thus, in the similar manner as the above described programming operation, programming before erasure is carried out. After the threshold voltage of the memory cell is raised, collective erasing operation is effected on all memory cells. In this operation, programming high voltage Vpp from the high voltage control circuit 30 is applied from array source switch 32 to source line SL, Y gate 20 is turned off, bit line BL is set to the floating state, and the potentials of the word lines are all set to 0 V. Thus electrons are ejected from all the floating gates of the memory cells to the source line SL, whereby the threshold voltage of the memory cell is decreased.
Generally, control signals required by control circuit 28 are generated by applying external control signals in the form of commands to control signal buffer 26 for carrying out programming before erasure and erasing operation.
(iii) Reading operation:
In reading operation, a control signal enabling reading is applied through control signal buffer 26 to control circuit 28. Consequently, array source switch 32 sets the source line SL to the ground potential, and high voltage switch 18 is set to the supply voltage Vcc selecting state. Address data EXA0 to EXAn designating addresses of the memory cells holding the information to be read are applied to address buffer 12. Correspondingly, one word line of memory array 10 is selected by row decoder 14, and selecting voltage VR at the level of the supply voltage Vcc is transmitted by high voltage switch 18 to the selected word line. Similarly, column decoder 16 generates a column selecting signal, and Y gate 20 connects the selected bit line to block 24 in response to the column selecting signal.
In block 24, the sense amplifier has been activated under the control of control circuit 28, and by applying read voltage to bit line BL and by detecting presence/absence of a current flowing through the bit line, data is read and the read data is applied to input/output buffer 22. In input/output buffer 22, the output buffer has been activated under the control of control circuit 28, and external read data is generated from the read data applied from sense amplifier (block 24) and the generated data is output.
Now, the necessity of programming before erasure will be described. Assume that collective erasure is effected without programming before erasure, as shown in FIG. 62.
Before collective erasure, the information stored in the memory cell is "0" or "1", and the threshold voltage Vth thereof is at "high state" or "low state" in accordance with the information stored therein.
Erasure of a memory cell is carried out by ejecting electrons from the floating gate electrically (in the form of tunneling current). Therefore, if a memory cell storing information "1" is erased, the threshold voltage thereof is so decreased as to have a negative value, causing "over erased" state. The "over erased" memory cell is normally at a conductive state, causing the following problem.
For the purpose of description, consider memory cells M01 to M33 arranged in four rows and three columns, as shown in FIG. 63. Word lines WLi (i=0.about.3) are provided for respective rows, and bit lines BLj (j=1.about.3) are provided for respective columns. Memory cells M01 to M33 have their sources commonly connected to the source line SL.
In the arrangement shown in FIG. 63, assume that memory cell M31 is at "over erased" state. When data stored in memory cell M21, which is information "1", is to be read, source line SL is connected to the ground potential and selecting voltage at the level of the supply voltage Vcc is transmitted to word line WL. The threshold voltage of memory cell M21 is sufficiently lower than the supply voltage Vcc, so that memory cell M21 is rendered conductive, and a current flows to bit line BL1 through memory cell M21. At this time, since the sense amplifier determines whether or not there is a current flowing through the bit line BL1, reading of information "1" is effected even when memory cell M31 is at the "over erased state" and is conductive.
When a memory cell M11 storing information "0" is to be selected, a voltage at the level of the supply voltage Vcc is transmitted to word line WL1. Since the threshold voltage of memory cell M11 is sufficiently higher than the supply voltage Vcc, memory cell M11 is kept at the non-conductive state. However, in this case, even if the potential on word line WL3 is at the ground potential level of 0 V, memory cell M31 is at the conductive state, and hence current flows through memory cell M31. Consequently, the information stored in memory cell M11 is erroneously determined to be "1", resulting in erroneous data reading.
More specifically, if even one of the memory cells connected to one bit line is at the "over erased" state and has negative threshold voltage, current flows to the bit line even if the "over erased" memory cell is not selected, and hence the information of the selected memory cell cannot be read correctly. In order to prevent occurrence of such "over erased" state, programming before erasure is carried out prior to collective erasure. More specifically, as shown in FIG. 64, information "0" is written to the memory cells of all addresses prior to collective erasure, so that the threshold voltages of the memory cells of all addresses are once set to high threshold voltage state, and then collective erasure is effected. For the programming before erasure, addresses are successively incremented externally or internally so as to successively designate all addresses, and information "0" is written to the memory cell corresponding to the designated address.
Since collective erasure is carried out after the threshold voltage of the memory cell of all addresses are once set to the high state, the threshold voltages of the memory cells of all addresses come to have positive values which are sufficiently lower than the supply voltage Vcc, which prevents generation of "over erased" state.
In most semiconductor memory devices, a defective word line or a defective bit line is replaced by a redundant word line or a redundant bit line so as to repair the defective word line or the defective bit line in equivalence, in order to improve production yield.
In a nonvolatile semiconductor memory device, when a defective memory cell which is at the above described "over erased" state is found during testing, for example, the defective memory cell can be repaired by replacing the bit line associated with the defective memory cell by a redundant bit line. If the defect includes short-circuit with adjacent bit line, it can be repaired by replacing the short-circuited defective bit lines by the redundant bit lines. However, when a word line which is formed of a metal interconnection is short-circuited with the adjacent word line because of a particle, a defective insulation film or residue of etching during manufacturing, the word line cannot be repaired generally.
Assume that word lines WL2 and WL3 are short circuited in FIG. 65. In FIG. 65, this short-circuited portion is represented by a circled resistive element R.
When the supply voltage Vcc is transmitted to word line WL2 for reading information, the potential of the selected word line WL2 decreases because of a leak path constituted by resistive element R, as the potential of the adjacent word line WL3 is at the ground potential level, so that the information stored in the memory cells connected to word line WL2 cannot be read correctly. Similarly, when a programming high voltage Vpp is transmitted to word line WL2 for writing information "0", the potential on word line WL2 decreases because of the leak path caused by resistive element R, so that information "0" cannot be written. This also applies to the selection of word line WL3.
Assume that such defective word lines WL2 and WL3 are replaced by redundant word lines WL21 and WL31. If such replacement takes place, word lines WL2 and WL3 are always kept at the non-selected state, and when word line WL2 or WL3 is addressed, word line WL21 or WL31 is selected. Consider erasing operation with such replacement. As mentioned before, programming before erasure is carried out before erasing operation. In this programming before erasure, word lines are successively selected, and the programming high voltage Vpp is transmitted to the selected word line.
However, since the word lines WL2 and WL3 are always kept at the non-selected state, programming before erasure cannot be effected on the memory cells connected to the word lines WL2 and WL3. Though it is possible to modify the circuit so that the defective word lines WL2 and WL3 are successively selected only in the programming before erasure, it is impossible to actually carry out programming before erasure of the memory cells connected to the word lines WL2 and WL3, since there is still the leak path (resistive element R) when the word lines WL2 and WL3 are selected separately.
After the programming before erasure, collective erasing operation is carried out. In this collective erasure, all the memory cells have their sources connected commonly to the source line SL. The high voltage Vpp is applied to the source line, and the ground potential is transmitted to all the word lines as in the non-selected state. Therefore, in this collective erasing operation, the memory cells connected to the defective word lines WL2 and WL3 are erased. That is, the memory cells M21 to M23 and M31 to M33 connected to the defective word lines WL2 and WL3 are erased without writing of information "1", so that these memory cells are set to over erased state.
Accordingly, even if the defective word lines WL2 and WL3 are replaced by the redundant word lines WL21 and WL31, the condition is the same as the above described example in which programming before erasure is not carried out. Thus the set of defective word lines including short-circuit cannot be repaired in the conventional redundancy configuration, and hence production yield cannot be improved.
A method of repairing neighboring defective word lines will be described with reference to the flow chart of FIG. 66. FIG. 66 shows an operation for testing whether the memory cell is defective or not.
Referring to FIG. 66, in the test operation mode, in accordance with an internally generated address or an externally applied address, one word line is selected (step S1). Then, by maintaining the selected word line at the selected state, a bit line is selected in accordance with a column address signal, and data of 1 bit of memory cell is read (step S2). In the testing operation, memory cells are all set to the erased state, and the data stored is "1".
Thereafter, whether the read data is "1" or not is determined (step S3). If there is a defect on the word line and the potential of the word line does not increase, the memory cell transistor does not turn on (in the initial state of testing, there is not the over erased state). If there is a defective word line, the read data would be "0". The address of the memory cell, the data read from which is "0", is stored (step S4).
If the read data is "1", it is determined that the potential of the word line is increased normally, and therefore it is determined whether or not the last bit line connected to the selected word line has been selected (step S5).
If the last bit line has not yet been selected, the bit line address is incremented by one (step S6). Then, steps S2 to S5 are carried out again.
In step S5, if the last bit line has been selected, the flow proceeds to the step S7 in which whether or not the word line which is set to the selected state is the last word line is determined. If it is not the last word line, the word line address is incremented by one (step S8), the flow returns to the step S1 for selecting the word line in accordance with the newly incremented word line address, and the steps S2 to S6 are repeated.
If it is determined in step S7 that the last word line has been selected, the address of the defective bit stored previously is analyzed (step S9). If all read data are "0" for a specific word line address, it is determined to be a short-circuit defect of the word line. The defective line cannot be repaired. The nonvolatile semiconductor memory device is discarded as defective device. If defective memory cells exist concentrated on a specific region of a specific word line, it is regarded as a disconnection of the word line. The defective word line cannot be repaired in this case either, and therefore the nonvolatile semiconductor memory device is discarded as the defective device.
If defective bits (memory cells) exist concentrated on a specific column, the bit line is replaced by a spare bit line.
When the above described method of detecting a defective word line is employed, it is necessary to determine whether the word line is defective or not by reading bit by bit the memory cell data. This results in considerably long time for testing.